The present invention relates to magnetic domain wall shift register memory devices, and more specifically, to a magnetic domain wall shift register memory device utilizing compactly stacked self-referencing magnetic tunnel junctions (MTJs) having improved readout characteristics.
Magnetic domain wall shift register memory, often referred to as racetrack memory (RTM), is a non-volatile magnetic memory device which utilizes magnetic domains to store data in a ferromagnetic nanowire configured as a shift register. Multiple magnetic domains, separated by domain walls, are shifted through the nanowire by short pulses of spin-polarized current along the nanowire. Data is stored in the magnetic polarization of the domains, which can be set by an injector such as a field-generating wire or a spin-torque-transfer device. One method of reading the data senses domain polarization with a magnetic tunnel junction (MTJ) adjacent to the magnetic nanowire. Arrays of nanowires oriented parallel to the substrate comprise “in-plane” racetrack memory (iRTM). iRTM offers a relatively dense alternative to other memories such as magnetoresistive random access memory (MRAM), flash, SRAM, phase change memory (PCM), and DRAM, with the added benefits of endurance and non-volatility.
State of the art iRTM includes one write and one read device per planar domain wall shift register track. The prior art details ways to stack layers of iRTM atop each other for higher memory density through better use of underlying silicon area. To allow for shifting domain walls and reading domains in a given plane of iRTM, stacked iRTM must locate transistors at the end of each track so that single tracks can be independently shifted and read. So, while the iRTM can be made denser through stacking, there is still a difficulty with densely packing transistors near the ends of the racetrack wires.
At present, other forms of memory may be more cost-effective and optimize area more efficiently than a single plane of iRTM. One contemplated solution is vertical racetrack memory (vRTM), which provides higher density memory through vertical orientation of the shift-register nanowires. However, vRTM has fabrication complexity that makes vRTM a currently unavailable solution.